CMOS Technology

According to Moore’s law, CMOS technology channel length is shrinking to improve speed and accommodate more features in a single die. Transistor, f_T is inversely proportional to channel length and has push device to run on GHz range. While continue pushing transistor speed, it has hit the power well of the device in 2003. It ultimately ended INTEL processor speed race with maximum speed of 4GHz processor in the market. INTEL is then making a 360˚ change to multi-core processor architecture and has pushed more features into a processor architecture design for power saving purposes. This includes North Bridge (memory control hub). Power can be reduced to half with two or more core-processors. Many-many core architecture will be the future trend for the processor which again emphasize on the importance of smaller channel length to reduce the transistor dimension to enabling the technology requirement.

However the scaling of the channel length is followed by gate oxide thickness and gate voltage scaling to maintain allowable electric field. Furthermore, power rail of the transistor is gradually decreased in order to save power. As Ids proportional to C_ox, Gate oxide thickness scaling is critical to increase the drive strength of the device from one generation to another generation. To increase C_ox, gate oxide thickness, T_ox need to be increased too. With T_ox of about 2 nm (equivalent to 20 atom size thickness) in 65 nm process technology, this has induced large amount of gate leakage current which caused by gate tunneling effect. It is estimated to have I_off of ~200 nA/μm with 15 nm of minimum channel length, Lmin. This contributes to huge static power in billion transistors System-on-Chip (SOC) product.

To solve this problem, high-K material is introduced to increase the gate oxide dielectric field constant. C_ox = E_rE_oA/T_ox, the equation shows how the material dielectric field constant, E_r can increase C_ox while giving more space for gate oxide thickness scaling. Currently, INTEL is using hafnium oxide to replace convention silicon oxide material which is able to increase E_r from 3.9 (silicon oxide) to 25 (hafnium oxide).

The disadvantages of using high K material with convention poly-si gate material are higher voltage threshold and poorer mobility. Higher voltage threshold gives design problem on lack of voltage headroom for circuitry design and slower switching response. This is a no no for high speed logic and analog design. The higher voltage threshold is due to Fermi level pinning at high K and poly-si interface. The poorer mobility of high k material with poly-si is due to the high k material phonon dipole in-resonance with plasma oscillation which can couple strongly into silicon channel and degrades the electron mobility. Therefore a metal, TiN act as metal work function with hafnium oxide are able to improve the channel electron mobility. Metal gate has opposite plasma oscillation and able to cancel or weakening the electric field in silicon channel and recover the mobility.

High K + metal gate device has achieved 50% I_sat/I_off ratio improvement on PMOS and 12% improvement on NMOS device compare to 65 nm process. While for gate leakage improvement, PMOS is 1000X better than 65 nm process PMOS. For threshold voltage rolloff, 45 nm technology High K + metal gate device scatter around 0.15-0.35V while 65 nm SiO2 + poly-si scatter around 0.35-0.55V. With lower threshold voltage, the device switches faster and stronger drive strength. It is general believe that high-K metal gate CMOS is the trend up to 22 nm process technology before tri-gate device with large parasitic issue can be resolved.