VLSI (Very Large Scaled Integrated Circuit) Design Flow

Pure-E final year 的大哥大姐请进~

请问analog integrated circuits 和 integrated VLSI system 的assignment 有什么分别？
都是用 mentor graphic 来 design circuit 吗？

哪 VLSI System Design and Modelling technique 又学些什么呢？
听说是与VHDL有关。
难道又是用FPGA Board 吗?

谢谢咯~

回复 1# ramen522 的帖子

没 有用过mentor graphic circuit and layout tools... industry 都是用cadence platform as analog/custom design flow... 给vlsi digital design flow , mentor graphic 的modelsim 是普遍的 industry tool... modelsim 都是vhdl/verilog compiler tool... 并有一些gate level optimization feature...通常vlsi digital design flow 有两种， 1）fpga implementation...for fast and easy implementation...基本上就只是写rtl code, 然后synthesize + place and route ( fpga 一条龙服务）。。2）asic design flow。。也就是要做rtl coding + synthesize + place and route + PC ( physical compiler) + clock buffer insertion + formal verification 等等完成一系列烦人的design process 后， 你就的convert 你的place and route 后generate 的layout to gds or cif for layout submission to foundries。。。既费时又费钱 （一次tape out cost million dollar) 如果中间有process 出错， 就的再搞多一次tape out, 又得再浪费million... 所以conclusion 是 fpga good for fast and easy implementation, any thing goest wrong, just reprogram fpga and synthesize again... but if go for mass production cost can be exp.... for asic design, if you go for mass production says for million units...asic design can be more cost effective than fpga...

那analog/custom design...又是另外一门totally diff 的学问。。analog design 基本上就是transistor level design...你以前在electronics 学到的common base/emitter/collector/gate/drain/source 等等，就的派上用场。。基本上就是用circuit entry tool （画circuit ) + circuit model simulation tool ( include your circuit netlist + transistor device model) 市面上常用的有hspice, pspice, spectra, orcad, 等等。。画好了，simulate后没问题，就要画layout ...市面上最常见的有cadence virtuoso layout tool...画好了layout , 你就要run drc ( design rule check ) + lvs ( layout vs. schematic check).. 确保没问题后， 你就可以convert layout to gds or cif file for layout submission to foundries.... 那就大功告成。。。

以上是在论坛里看了一个小孩的疑问后，所做出的回应。。呵呵。。看起来我太无聊了。。