my lucky nite
Debug了几个礼拜的mysterious bug原来就是。。原来真的就是fpga i/o failure,fpga竟然draw 400mA current..比正常下多了将近一倍。。这已经很不寻常了,只是之前一些control signal没问题。。所以没有怀疑到它身上。。直到星期5,确定了我的test chip 没问题, 开始重写fpga code, 竟然发现operation 有点问题。。当越多i/o activate, fpga开始操作不正常了。。所以很大可能fpga已经当掉了,可能是上个礼拜VCCINT regulator没有好好的ground...fpga sink了1A current.. 将i/o 搞掂了。。昨天跑去RIS换了一粒新的fpga,今天一试,ok了,不过还需要改下凌乱不堪的fpga code..现在果然work totally fine.. 明天可以放进chamber 做temperature test了。。高兴不可过5分钟。。接下来还有一大堆的东西要做。。不过始终还是放下了心头大石。。如果这个system board搞不掂,我可真的对不起众位同僚们。。test result out-> justification for gating issue -> enhancement -> technical paper...哈哈!希望年尾可以publish paper...
14 Comments:
Ooopps..........好像"鸡同鸭讲"。我读书少,不明白你讲什么??哈哈哈...别生气哦!!
呵呵!讲真我也不是很明白。paiseh~我是那些code code的白痴啦!嘻嘻。。。况且。。。哥哥,妹妹还小哦!^^
蕾蕾~
candy, 哈哈,这个我写给自己罢了咯。。一时兴奋嘛。。
forever, 好妹妹现在小,可是终归会变成大美人的。。你的好哥哥会等你的哦。。
你说的名词我一个都不明白。。阿哈
U r doing research on PHD course? O is ur project?
this is a proj.. i'm working on it.. hmm...i'm not sure whether u familiar to US engineering style or not.. phd topic is dig out from the proj you involved. same thing in engineering firm... technical paper is outcome of the proj solution... no proj-> no issue -> no solution -> no paper -> no value......
没戴眼镜的样子?呵呵~~旁边那个slide show 不是有大把咯~~你没看见哦?哈哈
sound like you are a bit prof,and i believe you got good memorize.Do you have better way to memory all the specification of products when i want doing presentation to my client?
anonymous, anyway to keep contact? this is a good topic man...haha... i mean, i won't memorize thing... when the stuff keep repeating..u will definitely remember... but i think you got to really be familiar with your product.. then only u can present it to your customer.. u can't force yourself to memorize something that u r not interested or not familiar with rite? just my little advice...
景景, 有吗??怎么没看到的。。。让我在去查查。。。
哈,fpga...我朋友在拿这个thesis题目。大学都很废下,到final year才给人touch一些从来都不知道‘么水’的东东。
janice, fpga不错啊。。干吗你不拿呢??fpga有些时候比microcontroller更好用。。不过你得学会vhdl or verilog..很多时候,我们都是先将product design implement在fpga后,如果销售好的话,或者要进行mass production,那样就可以直接将implement在fpga的verilog,直接synthesize as a single asic chip..
谁不想啊?听说那个lecturer的thesis很容易score的。上次我解释过了,我只有没有选择的选择。
完全看不明白!=.="!不过看你写得酱兴奋,不留言应酬下都不行,等下你又说为什么酱久没上来!
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